1. Field of the Invention
The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure having two dielectric layers in the same layer and a manufacturing method thereof.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a photo-mask pattern. The photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.
In recent years, with the increasing miniaturization of semiconductor devices, the design rule of line width and space between lines or devices becomes finer, for example down to feature sizes of 65 nanometers (nm), 45 nm and even to 32 nm. The width is subject to optical characteristics, however. To obtain fine-sized devices in the exposure, the interval between transparent regions in a mask is scaled down with device size. When the light passes through the mask, diffraction occurs and reduces resolution. Moreover, when light passes through the transparent regions of a mask having different interval sizes, the light through the regions having small interval sizes is influenced by the transparent regions having large interval sizes, resulting in deformation of the transfer pattern. For example, right-angled corner rounded phenomenon, line end shortened phenomenon, and line width increase/decrease phenomenon are well known defects resulting from OPE.
A double-exposure technique has been developed in recent years, which involves forming a target pattern by two exposure processes; however, the double-exposure technique still has some problems that need to be overcome.